1. Technical Field
The present invention relates generally to memory systems and more particularly, but not exclusively, to write recovery times of a volatile memory device.
2. Background Art
In the area of memories, dynamic random access memories (DRAMs) typically perform as the main memory of a computer system. That is, in a typical computer system, such as a desk top personal computer (PC), the main memory function is performed by DRAM devices. The operation of a DRAM is generally utilized with a processor, such as a central processing unit of a computer, but in other instances, the DRAM may be used with other processing/controlling devices, such as memory controllers.
In order to provide much higher performance in faster computer systems, higher performance requirements are also placed on DRAMs to process data in much larger quantities and in much faster performance time. Thus, it is not uncommon to find DRAMs configured into banks of DRAM arrays, in which data transfer to and from the DRAM arrays are achieved by high data speed bursts. For example, a high-speed 256 mega bit (Mb) DRAM, arranged in multiple banks, may be clocked to provide data transfer with an issuance of a read and/or write access command. It is also generally understood that DRAM devices utilize a precharge function. Precharging a DRAM generally refers to an operation that charges the bit lines to a preselected value. An auto-precharge condition automatically precharges the bit lines in response to an issuance of a command, such as a read or write command. That is, in some instances a read or write command may initiate an auto-precharge of the accessed bit lines prior to performing the read or the write function. With most DRAMs, the precharge or auto-precharge function typically has a signal sent from a processor or controller to the DRAM device in order to perform the precharging operation.
A write recovery parameter (tWR) represents a time required to store data into a DRAM (or other) cell before a subsequent precharge of the cell can take place. DRAMs historically have allowed 15 ns for tWR. However, with DRAM technology scaling to below 20 nm, tWR is expected to increase by three to five times current values—e.g. due to increased resistance in a path to a DRAM cell though data lines, sense amplifier circuitry, bit lines in the array, etc. Such increases in tWR will impact future CPU performance. For example, a 5% or more decrease in processor performance in server systems may be expected for a three time increase in tWR.